Synplify pro for win 8 code#

Likewise, you might have a signal with a name that suggests it connects to the output of a module, only to find that the signal is not actually connected in the design.

Its possible to do an entire design to carefully generate the inputs to the module, but then never actually use them. It is also common for a port to be connected to a signal with a similar name because of copy/paste. In your case, the input data port probably has a similar issue - it claims the input is not driven. In the above, Dout, d_out, and data_out all have similar names.

Synplify pro for win 8 code#

a glance at the code might suggest it has been. Dout hasn't been connected to either data_out or d_out. Often, this error is because of signal names being similar. But all it does is keep the unused ports and either ignores the unused inputs, and ties the constant outputs to 0's or 1's. If you disable logic removal (register removal, constant propogation, etc.), you'll get something that can be built. The pre-synthesis simulation screen shot is:īut the pos-tynthesis simulation always like this, what's wrong with it?Īlso, are you certain it works, or did it just stop giving build errors. So I guess there are some timing issues of the code. It passes through a flip-flop and Spi clock from MCU is always there. only 60% messages received correctly.Īdditionally, in the netlist, I can see the TP276 was not connected with input spi clock directly. TP259 toggled up and down which means sometimes current value is not same as the old value. I add test point in the code, found TP276 was lost sometimes (on scope), at the same time, TP272 just hold the old value. I set a predefined value to send to MCU, but on MCU side, I got a lot strange values, looks like random. This code can work but not stable, about 40% message goes to wrong. Output data on SPI_CLK rising edge, and sample at falling edge. MASTER_CLK at 20MHz, SPI working on 1MHz. Variable varRxData: std_logic_vector(63 downto 0) The main process could read SPI data from DATA_OUT and does some extra work. What I expected is that DATA_IN, DATA_OUT are connected with internal signal vectors. Only signals that connected to chip pins were remain even I have using syn_hier and syn_noprune:ĭATA_IN: in std_logic_vector(63 downto 0) ĭATA_OUT: out std_logic_vector(63 downto 0) Īttribute syn_noprune of SPI : component is true I found after compile, the netlist looks like this: It works perfect in pre-synthesis simulation but doesn't work on FPGA. SPI_READY: out std_logic - Spi transmit completeĭATA_IN: in std_logic_vector(63 downto 0) - Input data 8 bytesĭATA_OUT: out std_logic_vector(63 downto 0) - Output data 8 bytesĪttribute syn_hier of SPI_ONE: architecture is 'hard' SPI_RESET: in std_logic - Reset Spi processing The SPI was write as a sub-module, defined as follow: I am working on SPI implementation in my project, facing a problem that I thought was the optimization problem.